Semiconductor device having metal gate and manufacturing method thereof

ABSTRACT

A manufacturing method of a semiconductor device having metal gate includes providing a substrate having a first semiconductor device formed thereon, and the first semiconductor device includes a first dummy gate. Next, the dummy gate is removed to form a first gate trench in the first semiconductor device, and the substrate is exposed in a bottom of the first gate trench. Subsequently, an epitaxial channel layer is formed in the first gate trench.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a semiconductor device having metal gate andmanufacturing method thereof, and more particularly, to a semiconductordevice having metal gate and manufacturing method integrated withepitaxy technique.

2. Description of the Prior Art

With semiconductor processes entering the era of the deep submicronmeter, it has been more and more important to increase the metal-oxidesemiconductor (MOS) drive current. To improve device performance,epitaxy technique is developed to enhance carrier mobility of thechannel region.

On the other hands, with the trend toward scaling down the size of thesemiconductor device, work function metals are provided to replace theconventional polysilicon gate to be the control electrode that competentto the high dielectric constant (herein after abbreviated as high-K)gate dielectric layer. The metal gate methods in the-state-of-art arecategorized into the gate first process and the gate last process. Amongthe two main processes, the gate last process is able to avoid processesof high thermal budget and to provide wider material choices for thehigh-K gate dielectric layer and the metal gate, and thus the gate lastprocess gradually replaces the gate first process.

It is observed that processes with high thermal budget impacts not onlythe metal gate process, but also the quality of the epitaxial layers. Inthe view of the above, there exists a need for integrating the epitaxytechnique and metal gate process without encountering the high thermalbudget issue.

SUMMARY OF THE INVENTION

According to an aspect of the present invention, a manufacturing methodof a semiconductor device having metal gate is provided. According tothe manufacturing method, a substrate having at least a firstsemiconductor device formed thereon is provided, and the firstsemiconductor device includes a first dummy gate. Next, the first dummygate is removing to form a first gate trench in the first semiconductordevice, and the substrate is exposed in a bottom of the first gatetrench. After forming the first gate trench, an epitaxial channel layeris formed in the first gate trench.

According to an aspect of the present invention, a semiconductor devicehaving metal gate is provided. The semiconductor device includes asubstrate, a metal gate positioned on the substrate, a high-k gatedielectric layer, and an epitaxial channel layer positioned in betweenthe high-k gate dielectric layer and the substrate. A length of theepitaxial channel layer is equal to a length of the metal gate.

According to the semiconductor device having metal gate and themanufacturing method thereof provided by the present invention, themetal-last process is integrated with the epitaxy technique.Accordingly, the epitaxial channel layer is formed in the gate trenchafter performing steps having high thermal budget such as source/drainformation, and silicide process. And the metal gate is subsequentlyformed in the gate trench. Since the epitaxial channel layer and themetal gate are all formed after process requiring high temperature,qualities of the metal gate and the epitaxial channel layer are nolonger impacted by those processes and thus performance of thetransistor device is improved.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1-6 are drawings illustrating a manufacturing method for asemiconductor device having metal gate provided by a first preferredembodiment of the present invention, wherein

FIG. 2 is a schematic drawing in a step subsequent to FIG. 1,

FIG. 3 is a schematic drawing in a step subsequent to FIG. 2,

FIG. 4 is a schematic drawing in a step subsequent to FIG. 3,

FIG. 5 is a schematic drawing in a step subsequent to FIG. 4, and

FIG. 6 is a schematic drawing in a step subsequent to FIG. 5.

FIGS. 7-10 are drawings illustrating a manufacturing method for asemiconductor device having metal gate provided by a second preferredembodiment of the present invention, wherein

FIG. 8 is a schematic drawing in a step subsequent to FIG. 7,

FIG. 9 is a schematic drawing in a step subsequent to FIG. 8, and

FIG. 10 is a schematic drawing in a step subsequent to FIG. 9.

DETAILED DESCRIPTION

Please refer to FIGS. 1-6, which are drawings illustrating amanufacturing method for a semiconductor device having metal gateprovided by a first preferred embodiment of the present invention. Asshown in FIG. 1, the preferred embodiment first provides a substrate 100such as silicon substrate, silicon-containing substrate, orsilicon-on-insulator (SOI) substrate. The substrate 100 includes a coreregion 102 and a peripheral region 104 defined thereon. An isolationstructure 106, such as a shallow trench isolation (STI) is formed in thesubstrate 100 between the core region 102 and the peripheral region 104for rendering electrical isolation. A first semiconductor device 110 isformed in the core region 102 and a second semiconductor device 112 isformed in the peripheral region 104. In the preferred embodiment, thefirst semiconductor device 110 and the second semiconductor device 112include the same conductivity type. However, those skilled in the artwould easily realize that the first semiconductor device 110 and thesecond semiconductor device 112 can include conductivity types that arecomplementary to each other. Additionally, semiconductor devices havingconductivity types complementary to the first semiconductor device 110can be formed in the core region 102, but not detailed.

Please still refer to FIG. 1. The first semiconductor device 110 and thesecond semiconductor device 112 respectively includes an oxide layer114, a dummy gate 116 such as a polysilicon layer formed on the oxidelayer 114, and a patterned hard mask (not shown) formed on the dummygate 116 for defining placement of the dummy gate 116. As shown in FIG.1, the oxide layer 114 is formed between the dummy gate 116 and thesubstrate 100 for serving as an interfacial layer (IL). Theintentionally grown interfacial layer is used in order to arrange a goodinterface between the surface of the substrate 100 and the gateinsulator, particularly the high-k gate insulator, formed later. Theoxide layer 114 is formed on the substrate 100 by high-temperatureprocess such as in-situ silicon growth (ISSG), rapid thermal oxidation(RTO), etc. The first semiconductor device 110 and the secondsemiconductor device 112 further respectively include first lightlydoped drains (hereinafter abbreviate as LDDs) 120 and second LDDs 122, aspacer 124, a first source/drain 130 and a second source/drain 132.Salicides (not shown) are respectively formed on the first source/drain130 and the second source/drain 132. After forming the firstsemiconductor device 110 and the second semiconductor device 112, acontact etch stop layer (hereinafter abbreviated as CESL) 140 and aninter-layer dielectric (hereinafter abbreviated as ILD) layer 142 aresequentially formed. Since the steps and material choices for theabovementioned elements are well-known to those skilled in the art,those details are omitted herein in the interest of brevity.

Furthermore, selective strain scheme (SSS) can be used in the preferredembodiment. For example, a selective epitaxial growth (hereinafterabbreviated as SEG) method can be used to form at least the firstsource/drain 130. Accordingly, the first source/drain 130 of the firstsemiconductor device 100 in the core region 102 respectively includes adoped epitaxial layer. Because the lattice constant of the epitaxiallayer is different from that of the silicon substrate, a strained stressis generated and a surface of the first source/drain 130 having thedoped epitaxial layer may be higher than a surface of the substrate 100,as shown in FIG. 1.

Please refer to FIGS. 1 and 2. After forming the CESL 140 and the ILDlayer 142, a planarization process is performed to remove a portion ofthe CESL 140 and a portion of the ILD layer 142 to expose the patternedhard masks or the dummy gates 116 of the first semiconductor device 110and the second semiconductor device 112. Subsequently, a suitableetching process is performed to remove the patterned hard masks and thedummy gates 116 of the first semiconductor device 110 and the secondsemiconductor device 112. Consequently, a first gate trench 150 isformed in the first semiconductor device 110 and a second gate trench152 is simultaneously formed in the second semiconductor device 112. Asshown in FIG. 2, the oxide layers 114 are exposed in bottoms of both thefirst gate trench 150 and the second gate trench 152.

Please refer to FIG. 3. More important, an etching process is performedto remove the oxide layer 114 from the first gate trench 150 with asuitable etchant after forming the first gate trench 150 and the secondgate trench 152. It should be understood that a protection layer (notshown) can be formed in the second semiconductor device 112 in order toprotect the oxide layer 114 exposed in the bottom of the second gatetrench 152. Consequently, the substrate 100 is exposed in the bottom ofthe first gate trench 150 while the oxide layer 114 is exposed in thebottom of the second gate trench 152 according to the preferredembodiment. However, those skilled in the art would easily realize thatthe oxide layers 114 can be simultaneously removed from both of thefirst gate trench 150 and the second gate trench 152 according to amodification to the preferred embodiment, and thus the substrate 100 isexposed in the bottoms of both the first gate trench 150 and the secondgate trench 152.

Please refer to FIG. 4. After removing the oxide layer 114 from thefirst gate trench 150 to expose the substrate 100, a cleaning step isperformed to remove native oxides or other impurities from the firstgate trench 150. Next, an epitaxy process, such as a SEG method isperformed to form an epitaxial channel layer 160 in the first gatetrench 150. A thickness of the epitaxial channel layer 160 is between 2nanometer (hereinafter abbreviated as nm) and 50 nm. Because theepitaxial materials only grow along the silicon surface, the epitaxialchannel layer 160 is spontaneously formed on the exposed substrate 100and confined within the first gate trench 150. Additionally, a bottom ofthe epitaxial channel layer 160 is coplanar with the surface of thesubstrate 100. It is noteworthy that the epitaxial channel layer 160includes different materials depending on the conductivity type requiredin the preferred embodiment. For example, when the first semiconductordevice 110 is a p-typed semiconductor device, the epitaxial channellayer 160 includes silicon (Si), germanium (Ge), or silicon germanium(SiGe). When the first semiconductor device 110 is an n-typedsemiconductor device, the epitaxial channel layer 160 includes III-Vmaterial such as gallium arsenide (GaAs), indium phosphide (InP), indiumarsenide (InAs), or indium antimonide (InSb). Additionally, theepitaxial channel layer 160 can include doped epitaxial material orundoped epitaxial material. When the epitaxial channel layer 160includes the doped epitaxial material, it further includes dopantshaving conductivity type complementary to the first source/drain 130.

Please refer to FIG. 5. After forming the epitaxial channel layer 160, ahigh-k gate dielectric layer 170 is formed on the substrate 100. It istherefore conceivable that the preferred embodiment adopts the high-klast process. The high-k gate dielectric layer 170 can include metaloxides such as rare earth metal oxides. The high-k gate dielectric layer170 can include material selected from the group consisting of hafniumoxide (HfO₂), hafnium silicon oxide (HfSiO₄), hafnium silicon oxynitride(HfSiON), aluminum oxide (Al₂O₃), lanthanum oxide (La₂O₃), tantalumoxide (Ta₂O₅), yttrium oxide (Y₂O₃), zirconium oxide (ZrO₂), strontiumtitanate oxide (SrTiO₃), zirconium silicon oxide (ZrSiO₄), hafniumzirconium oxide (HfZrO₄), strontium bismuth tantalate, (SrBi₂ Ta₂O₉,SBT), lead zirconate titanate (PbZr_(x)Ti_(1−x)O₃, PZT), and bariumstrontium titanate (Ba_(x)Sr_(1−x)TiO₃, BST).

Please still refer to FIG. 5. After forming the high-k gate dielectriclayer 170, a work function metal layer 172 and a filling metal layer 174are sequentially formed on the substrate 100. As shown in FIG. 5, thefirst gate trench 150 and the second gate trench 152 are filled up withthe filling metal layer 174. The work function metal layer 172 includesdifferent metal materials depending on the conductivity type required inaccordance with the preferred embodiment. For example, when the firstsemiconductor device 110 is a p-typed semiconductor device, the workfunction metal layer 172 includes p-metal and possesses a work functionbetween 4.8 and 5.2. When the first semiconductor device 110 is ann-typed semiconductor device, the work function metal layer 172 includesan n-metal and possesses a work function between 3.9 and 4.3.Furthermore, it is well-known to those skilled in the art that otherlayers such as the barrier layer, the etch stop layer, or, even thestrained layer can be formed in the gate trenches 150/152 before formingthe work function metal layer 172.

Please refer to FIG. 6. Next, a planarization process, such as achemical mechanical polishing (CMP) process is performed to remove thesuperfluous filling metal layer 174, work function metal layer 172, andthe high-k gate dielectric layer 170. Consequently, a first metal gate180 is formed in the first semiconductor device 110 and a second metalgate 182 is formed in the second semiconductor device 112. In addition,the ILD layer 140 and the CESL 142 can be selectively removed andsequentially reformed on the substrate 100 for improving performance ofthe semiconductor devices 110/112 in the preferred embodiment. As shownin FIG. 6, since the preferred embodiment adopts the high-k lastprocess, the high-k gate dielectric layer 170 includes a U shape. Moreimportant, the epitaxial channel layer 160 is formed between the high-kgate dielectric layer 170 and the substrate 100, and confined within thespacer 124. A length of the epitaxial channel layer 160 is equal to alength of the firs metal gate 180.

According to the semiconductor having metal gate and manufacturingmethod thereof provided by the first preferred embodiment, the gate-lastprocess and epitaxy technique are integrated successfully. Moreimportant, the epitaxial channel layer 160 is formed in the first gatetrench 150 after the processes having high thermal budget, such as theoxide layer 114 formation, the source/drain 130 formation, and thesilicide process. And the metal gates 180/182 are subsequently formed.Since the epitaxial channel layer 160 and the metal gates 180/182 areall formed after the high temperature processes, qualities of theepitaxial channel layer 160 and the metal gates 180/182 are no longerimpacted and thus the performance of the first semiconductor device 110is improved.

Please refer to FIGS. 7-10, which are drawings illustrating amanufacturing method for a semiconductor device having metal gateprovided by a second preferred embodiment of the present invention. Itshould be noted that elements the same in both of the first and secondpreferred embodiments can include the same material and conductivitytype, and therefore those details are omitted in the interest ofbrevity. As shown in FIG. 7, the preferred embodiment first provides asubstrate 200. The substrate 200 includes a core region 202 and aperipheral region 204 defined thereon. An isolation structure 206, suchas a shallow trench isolation is formed in the substrate 200 between thecore region 202 and the peripheral region 204 for rendering electricalisolation. A first semiconductor device 210 is formed in the core region202 and a second semiconductor device 212 is formed in the peripheralregion 204. As mentioned above, the first semiconductor device 210 andthe second semiconductor device 212 include the same conductivity type.However, those skilled in the art would easily realize that the firstsemiconductor device 210 and the second semiconductor device 212 caninclude conductivity types that are complementary to each other.Additionally, semiconductor devices having conductivity typescomplementary to the first semiconductor device 210 can be formed in thecore region 202, but not detailed.

Please still refer to FIG. 7. The first semiconductor device 210 and thesecond semiconductor device 212 respectively includes an oxide layer214, a dummy gate (not shown), and a patterned hard mask. As mentionedabove, the oxide layer 214 is formed between the dummy gate and thesubstrate 200 for serving as an interfacial layer. The intentionallygrown interfacial layer is used in order to arrange a good interfacebetween the surface of the substrate 200 and the gate insulator,particularly the high-k gate insulator, formed later. As mentionedabove, the oxide layer 214 is formed on the substrate 200 byhigh-temperature process such as ISSG, RTO, etc. The first semiconductordevice 210 and the second semiconductor device 212 respectively includefirst LDDs 220 and second LDDs 222, a spacer 224, a first source/drain230 and a second source/drain 232. Salicides (not shown) arerespectively formed on the first source/drain 230 and the secondsource/drain 232. After forming the first semiconductor device 210 andthe second semiconductor device 212, a CESL 240 and an ILD layer 242 aresequentially formed. Since the steps and material choices for theabovementioned elements are well-known to those skilled in the art,those details are omitted herein in the interest of brevity.

Furthermore, selective strain scheme (SSS) can be used in the preferredembodiment. For example, a SEG method can be used to form at least thefirst source/drain 230. Accordingly, the first source/drain 230 of thefirst semiconductor device 200 in the core region 202 respectivelyincludes a doped epitaxial layer. Because the lattice constant of theepitaxial layer is different from that of the silicon substrate, astrain stress is generated and a surface of the first source/drain 230having the doped epitaxial layer may be higher than a surface of thesubstrate 200, as shown in FIG. 7.

Please refer to FIG. 7. After forming the CESL 240 and the ILD layer242, a planarization process is performed to remove a portion of theCESL 240 and a portion of the ILD layer 242 to expose the patterned hardmasks or the dummy gates of the first semiconductor device 210 and thesecond semiconductor device 212. Subsequently, a suitable etchingprocess is performed to remove the patterned hard masks and the dummygates of the first semiconductor device 210 and the second semiconductordevice 212. Consequently, a first gate trench 250 is formed in the firstsemiconductor device 210 and a second gate trench 252 is simultaneouslyformed in the second semiconductor device 212. As shown in FIG. 7, theoxide layers 214 are exposed in bottoms of both the first gate trench250 and the second gate trench 252.

Please refer to FIG. 8. Next, an etching process is performed to removethe oxide layer 214 from the first gate trench 250 with a suitableetchant. Consequently, the substrate 200 is exposed in the bottom of thefirst gate trench 250 after removing the oxide layer 240. Moreimportant, the etching process is performed to over etch the substrate200 exposed in first gate trench 250, and thus a recess 254 is formed inthe bottom of the first gate trench 250. It should be understood that aprotection layer (not shown) can be formed in the second semiconductordevice 212 in order to protect the oxide layer 214 exposed in the bottomof the second gate trench 252. Consequently, the substrate 200 isexposed in the bottom of the first gate trench 250, particularly exposedin a bottom of the recess 254, while the oxide layer 214 is exposed inthe bottom of the second gate trench 252 according to the preferredembodiment. However, those skilled in the art would easily realize thatthe oxide layers 214 in both of the first gate trench 250 and the secondgate trench 252 can be simultaneously removed according to amodification to the preferred embodiment, and thus the substrate 200 isexposed in the bottoms of both the first gate trench 250 and the secondgate trench 252 and is over etched to form recesses respectively in thebottom of both the first gate trench 250 and the second gate trench 252.

Please refer to FIG. 9. After removing the oxide layer 214 and formingthe recess 254, a cleaning step is performed to remove native oxides orother impurities from the recess 254. Next, an epitaxy process, such asa SEG method is performed to form an epitaxial channel layer 260 in thefirst gate trench 250. A thickness of the epitaxial channel layer 260 isbetween 2 nm and 50 nm. Because the epitaxial materials only grow alongthe silicon surface, the epitaxial channel layer 260 is spontaneouslyformed on the exposed substrate 200 and confined within the first gatetrench 250. Additionally, a bottom of the epitaxial channel layer 260 isnon-coplanar with the surface of the substrate 200. As shown in FIG. 9,the epitaxial channel layer 260 is confined within the spacer 224, and abottom of the epitaxial channel layer 260 is lower than the surface ofthe substrate 200. As mentioned above, the epitaxial channel layer 260includes different materials depending on the conductivity type requiredin the preferred embodiment. Since the materials have been disclosed inthe first preferred embodiment, those details are omitted forsimplicity. Additionally, the epitaxial channel layer 260 can includedoped epitaxial material or undoped epitaxial material. When theepitaxial channel layer 260 includes the doped epitaxial material, itfurther includes dopants having conductivity type complementary to thefirst source/drain 230.

Please refer to FIG. 10. After forming the epitaxial channel layer 260,a high-k gate dielectric layer 270 is formed on the substrate 200. Thematerials used to form the high-k gate dielectric layer 270 are the samewith those detailed in the first preferred embodiment, therefore thosematerials are omitted for simplicity. It is therefore conceivable thatthe preferred embodiment adopts the high-k last process. After formingthe high-k gate dielectric layer 270, a work function metal layer 272and a filling metal layer 274 are sequentially formed on the substrate200. As shown in FIG. 10, the first gate trench 250 and the second gatetrench 252 are filled up with the filling metal layer 274. In thepreferred embodiment, the work function metal layer 272 includesdifferent metal materials depending on the conductivity type required inaccordance with the preferred embodiment. For example, when the firstsemiconductor device 210 is a p-typed semiconductor device, the workfunction metal layer 272 includes p-metal and possesses a work functionbetween 4.8 and 5.2. When the first semiconductor device 210 is ann-typed semiconductor device, the work function metal layer 272 includesan n-metal and possesses a work function between 3.9 and 4.3.Furthermore, it is well-known to those skilled in the art that otherlayers such as the barrier layer, the etch stop layer, or, even thestrained layer can be formed in the gate trenches 250/252 before formingthe work function metal layer 272.

Please still refer to FIG. 10. Next, a planarization process, such as aCMP process is performed to remove the superfluous filling metal layer274, work function metal layer 272, and the high-k gate dielectric layer270. Consequently, a first metal gate 280 is formed in the firstsemiconductor device 210 and a second metal gate 282 is formed in thesecond semiconductor device 212. In addition, the ILD layer 240 and theCESL 242 can be selectively removed and sequentially reformed on thesubstrate 200 for improving performance of the semiconductor devices210/212 in the preferred embodiment. As shown in FIG. 10, since thepreferred embodiment adopts the high-k last process, the high-k gatedielectric layer 270 includes a U shape. More important, the epitaxialchannel layer 260 is formed between the high-k gate dielectric layer 270and the substrate 200, and confined within the spacer 224. A length ofthe epitaxial channel layer 260 is equal to a length of the firs metalgate 280.

According to the semiconductor having metal gate and manufacturingmethod thereof provided by the second preferred embodiment, thegate-last process and epitaxy technique are integrated successfully.More important, the epitaxial channel layer 260 is formed in the firstgate trench 250 after the processes having high thermal budget, such asthe oxide layer 214 formation, the source/drain 230 formation, and thesilicide process. And the metal gates 280/282 are subsequently formed.Since the epitaxial channel layer 260 and the metal gates 280/282 areall formed after the high temperature processes, qualities of theepitaxial channel layer 260 and the metal gates 280/282 are no longerimpacted and thus the performance of the first semiconductor device 210is improved. Furthermore, since the bottom of the epitaxial channellayer 260 is lower than the surface of the substrate 200, the channelregion obtains more effective strained stress from the firstsource/drain 230 having the doped epitaxial material, and thus theperformance of the first semiconductor device 210 is further improved.

According to the semiconductor device having metal gate and themanufacturing method thereof provided by the present invention, themetal-last process is integrated with the epitaxy technique.Accordingly, the epitaxial channel layer with the bottom coplanar ornon-coplanar with the substrate is formed in the gate trench after stepsof high thermal budget such as source/drain formation, and silicideprocess. And the metal gate is subsequently formed in the gate trench.Since the epitaxial channel layer and the metal gate are all formedafter the processes having high thermal budget, qualities of the metalgate and the epitaxial channel layer are no longer impacted by thoseprocesses. For example, high resistance and current leakage due to thehigh thermal issue are all avoided and thus performance of thetransistor device is improved. Additionally, the semiconductor deviceand the manufacturing method thereof provided by the present inventioncan be integrated with multi-gate technique, such as the fin fieldtransistor (FinFET) technique.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention. Accordingly, the abovedisclosure should be construed as limited only by the metes and boundsof the appended claims.

1. A manufacturing method of a semiconductor device having metal gatecomprising: providing a substrate having at least a first semiconductordevice formed thereon, the first semiconductor device comprising a firstdummy gate; removing the first dummy gate to form a first gate trench inthe first semiconductor device, and the substrate is exposed in a bottomof the first gate trench; and forming an epitaxial channel layer in thefirst gate trench.
 2. The manufacturing method of the semiconductordevice having metal gate according to claim 1, further comprising anoxide layer formed between the substrate and the first dummy gate. 3.The manufacturing method of the semiconductor device having metal gateaccording to claim 2, further comprising removing the oxide layer toexpose the substrate in the bottom of the first gate trench afterremoving the first dummy gate.
 4. The manufacturing method of thesemiconductor device having metal gate according to claim 1, furthercomprising over etching the substrate exposed in the bottom of the firstgate trench.
 5. The manufacturing method of the semiconductor devicehaving metal gate according to claim 1, wherein the first semiconductordevice is a p-typed semiconductor device and the epitaxial channel layercomprises Si, Ge, or SiGe.
 6. The manufacturing method of thesemiconductor device having metal gate according to claim 1, wherein thefirst semiconductor device is an n-typed semiconductor device and theepitaxial channel layer comprises III-V material.
 7. The manufacturingmethod of the semiconductor device having metal gate according to claim1, further comprising a second semiconductor device positioned on thesubstrate, the second semiconductor device comprising a second dummygate and an oxide layer, and the oxide layer being positioned betweenthe second dummy gate and the substrate.
 8. The manufacturing method ofthe semiconductor device having metal gate according to claim 7, furthercomprising removing the second dummy gate to form a second gate trenchin the second semiconductor device simultaneously with removing thefirst dummy gate.
 9. The manufacturing method of the semiconductordevice having metal gate according to claim 8, wherein the oxide layeris exposed in a bottom of the second gate trench.
 10. The manufacturingmethod of the semiconductor device having metal gate according to claim1, further comprising forming a high dielectric constant (high-k) gatedielectric layer on the epitaxial channel layer.
 11. The manufacturingmethod of the semiconductor device having metal gate according to claim10, further comprising sequentially forming a work function metal layerand a filling metal layer on the high-k gate dielectric layer, and thefirst gate trench being filled up with the filling metal layer.
 12. Asemiconductor device having metal gate, comprising: a substrate; a metalgate positioned on the substrate; a high-k gate dielectric layer; and anepitaxial channel layer positioned in between the high-k gate dielectriclayer and the substrate, and a length of the epitaxial channel layer islarger than a length of the metal gate.
 13. The semiconductor devicehaving metal gate according to claim 12, wherein the high-k gatedielectric layer comprises a U shape.
 14. The semiconductor devicehaving metal gate according to claim 12, wherein the metal gatecomprises at least a work function metal layer and a filling metallayer.
 15. The semiconductor device having metal gate according to claim12, wherein the semiconductor device is a p-typed semiconductor deviceand the epitaxial channel layer comprises Si, Ge, or SiGe.
 16. Thesemiconductor device having metal gate according to claim 12, whereinthe semiconductor device is an n-typed semiconductor device and theepitaxial channel layer comprises III-V material.
 17. The semiconductordevice having metal gate according to claim 12, further comprising asource/drain formed in the substrate.
 18. The semiconductor devicehaving metal gate according to claim 17, wherein the source/draincomprises a doped epitaxial layer, respectively.
 19. The semiconductordevice having metal gate according to claim 12, wherein a bottom of theepitaxial channel layer and the substrate are coplanar.
 20. Thesemiconductor device having metal gate according to claim 12, wherein abottom of the epitaxial channel layer and the substrate arenon-coplanar.